1. Field of the Invention
The present invention relates to a moving picture decoding processor for multimedia signal processing. In more detail, it relates to a moving picture decoding processor, based on RISC(Reduced Instruction Set Computer) processor, having a separate bus structure to minimize memory access. And thus, it can provide optimized systems for various application fields.
2. Description of the Related Art
Recently, as the multimedia-and-network-related technology has been developed, the concept of communication is no more limited to the voice transmission and/or simple data transmission but enlarged to a multidimensional scale including a moving picture signal and a complex media such as an Internet.
In particular, with the standards being established by organizations such as the International Telecommunication Union(ITU) or the International Standardization Organization(ISO), the demand for moving picture signal transmission is about to be highly increased.
The standards, that have been established up to now, for moving picture signal processing are JPEG(Joint Photographic Experts Group) by ISO, H.261/H.263 by ITU, and MPEG(Moving Pictures Experts Group) series by ISO.
They have different characteristics for different application fields respectively. JPEG is mainly applied to photo-CD, H.261/H.263 are to video phone and video conference, MPEG-1 is to CD-ROM, CD-I and computer application, and MPEG-2 is to digital broadcasting and video distribution.
In particular, MPEG-4 is established in 1998 for the purpose of setting a coding standard for a complex multimedia including a static picture, computer graphics, voice coding of analytic synthesizer, and a synthesized audio and text by MIDI(Musical Instrument Data Interface) as well as compressing and coding the conventional audio and moving picture signals. MPEG-4 covers a wide range of data from a simple profile of 64 Kbps to a main profile of 38.4 Mbps so that it can handle all the application fields of multimedia.
Moreover, as IMT-2000 technology, a so-called the 4-th generation telecommunication technology, is gradually universalized, a multimedia telecommunication integrating voices and moving pictures is about to replace the currently used conventional voice and data telecommunication.
Since MPEG-4 is currently being used as a core of these next-generation technologies, its importance is being increased.
In distinction from other moving picture signal processing technologies, MPEG-4 is employed in wireless communication circumstances. Particularly, considering that the application field of simple profile is portable terminal, it has to be emphasized that MPEG-4 can be embodied by a small-size circuit and provide stronger error resilience and lower power consumption compared with other moving picture signal processing technologies.
FIG. 1 is a view illustrating the structure of a general media processor used for moving picture processing.
A main processor(101) is a controller working as a CPU, and it controls overall input/output and internal operations of a media processor(109).
Main processor has a limitation in its application fields, however, it has a characteristic that it can be modified and/or changed to perform some specific functions by various algorithms and upgrade itself thereby. So, it is generally designed to have a programmable structure rather than a fixed structure optimized for a specific function.
With this characteristic, a main processor(101) can execute a coded program designed for a specific function by using an internal program memory or an extra external memory.
The program is designed to perform various functions such as coding/decoding the basic moving picture signals, coding/decoding the voice signals, processing the interrupt signals generated by various peripheral devices, controlling for video display and video capture, communicating with a processor that works as an external host, separating the input voice/moving picture signals, and so on.
A main processor(101) is interfaced to the other blocks through a main bus(108), and the connection between the main processor(101) and the other blocks is controlled and arranged by bust arbitration.
The video capture section(102) receives moving picture signals through an external moving picture input device like a digital camera and stores them in a frame memory for encoding.
The video display section(103) transmits decoded moving picture signals to an external output device like an LCD.
All the decoding processes of moving picture signals are carried out by internal CODEC, however, various post processing can be performed at video display section(103) such as improving the screen resolution of decoded moving picture signals, controlling the size and the reference location of output moving picture, converting the format according to the type of output device, and so on.
A host interface(104) is used for the communication with an external host processor that controls the media processor(109) in FIG. 1 as a slave.
Generally, a host processor is a base band MODEM processor under the wireless communication circumstances, and it only carries out transferring the compound voice/moving picture signal, inputted from the interface with RF module and/or external devices, to the media processor(109).
An external memory interface(105) is used for interfacing with externally equipped memories, and generally includes a memory controller.
A video/audio CODEC(106) carries out coding/decoding voice/moving picture signals.
The video/audio CODEC(106) is the one in which an optimized coding/decoding algorithm is embodied by hardware and/or software in accordance with the application field of the media processor(109).
Peripheral devices(107) are additional devices for providing various interfaces of the system in which the media processor is being used, and generally include an inter IC controller(TIC), a timer, an universal asynchronous receiver/transmitter(UART), a clock controller, an interrupt controller, etc.
However, the above described media processor(109) has the following problems:
First, since the interfaces between the main processor(109) and the other blocks are formed by using only a single main bus(108), the load on the main bus(108) becomes larger and thus, it is difficult to improve the operation frequency.
Second, since the increase of main bus(108) load directly causes the increase of overall power consumption, the processor has difficulties in being applied to some application fields like a portable terminal.
Third, since all the blocks are interfaced by a main bus(108), the resource allocation of each block becomes inefficient.